22nmFinFETProcessFlow.pdf

22nm Gate Last FinFET Process Flow

22nm FinFet Process Flow

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The starting material for this type of process consists of <100> heavily doped P+ Silicon with a typical resistively of 0.01 Ω-cm. The front-side of the wafers have an ~1 μm thick layer of Epitaxial Silicon which has a resistively of approximately 14Ω-cm.

The wafers are cleaned with Piranha + HF + SC1+ SC2 and 50Å of pad
oxide is grown across their surface.
The most common cleaning agents are: Piranha - to remove organics SC1 - to remove particles SC2 to remove heavy metals Hydrofluoric acid (HF) to remove silicon dioxide

Screen Oxide Growth:

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N-Well and P-Well Definition:

The wafers are primed in HMDS and then coated with BARC and photoresist. After development the photoresist has a pattern that covers the region where the N-Well will be located.

Next, the exposed region of the wafers are implanted with Boron (mid-E13@10KeV, 7°) to define the P-Well.

The photoresist from the previous operation is stripped and the wafers are cleaned in Piranha.

The wafers are then primed in HMDS and again coated with BARC and photoresist. After development the photoresist has a pattern that covers the region where the P-Well is located.

Next, the exposed region of the wafers are implanted with Phosphorus(mid-E13@10-30KeV, 7°) to define the N-Well).

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Photoresist Strip & Pad Oxide Growth:

The photoresist from the previous operation is stripped and the wafers are cleaned in Piranha. The screen oxide is then stripped in Hydrofluoric acid (HF).

Following the well implants, the wafers undergo an Rapid Thermal Anneal (RTA) at 1,000 °C for 10 seconds to activate the implanted dopants in the wells.

The wafers are cleaned with Piranha + HF + SC1+ SC2 and 100 Å of pad oxide is grown across their surface.

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Rapid Thermal Processing is a key enabling technology that is required in order to make lon Implantation work.

It is not enough to simply implant dopant atoms into a silicon wafer. The dopant atoms must be "activated".

Activation is the process of causing the dopant atoms to move onto substitutional sites in the silicon lattice and become electrically active, modifying the Silicon's electrical characteristics.

Activation requires that the wafers be heated to a high temperature, usually from 1,000 - 1,350°C.

However, it is extremely important that the activation process not involve a lot of heat or the heat energy will cause the dopant atoms to diffuse into undesired regions of the wafer.

RTP solves this problem by raising the temperature to the activation point and then rapidly dropping it back down again. It does this so rapidly that the wafers do not have time to heat up.

The RTP equipment consists of an array of high-intensity lamps that heat up very rapidly and impart an short, abrupt flash of thermal energy to the front side of the wafer that does not involve a lot of heat.

Rapid Thermal Processing (RTP):

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梵

The current generation of lithography tool employs argon fluoride light with a wavelength of 193nm.

•By employing a wide rage of lithography of lithography “cheats" such as lens immersion lithography, Resolution Enhancement Technology (RET), Optical Proximity Correction (OPC), photoresist trimming etc., it is possible to print down to ~ 30nm with 193i lithography tools.

Extreme Ultra Violet (EUV) tools use a wavelength of 13.5nm and should be capable (using enhancement technologies) of printing features much smaller than this wavelength.

However, photons in the 13.5 nm range are soft X-rays and this poses a series of extremely challenging technical obstacles such as:

the entire tool must be in a hard vacuum

• EUV cannot use optical lenses and requires spherical mirrors to focus the beam

the EUV light sources are currently far to weak for a production tool and currently EUV lithography is capable of patterning only ~43 wafers per hour

extreme sensitivity to mask defects

However, 22nm FinFET require fins with dimensions as small as 10nm. Such punishing dimensions cannot be realized with 193i lithography technology and EUV is not available in 2013 and is unlikely to be available for the next two years.

The cost of a fully configured Extreme Ultra-Violet (EUV) Next Generation Lithography (NGL) stepper is $96 million. To put this in perspective, a Boeing 737 airliner cost approximately $35 million.

Depending on the product mix, a state-of-the-art semiconductor fab could require a minimum of 10 or more EUV steppers.

EUV is Not Available:

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